MBMap Registry
  1. Devices
  2. Alfa Instrumentos
  3. 3000C / 3000C.S

Alfa Instrumentos 3000C / 3000C.S Modbus register map

Also covers 3101C.S, 3102C.S, 3103C.S, 3104C, 3104C.S, 3105C, 3105C.S, 3107C, 3107C.S

Weighing indicators with Modbus RTU

  • Official
  • 97 registers
  • Modbus RTU
  • Revision 1 · 2026-10-20

Official: Written from the manufacturer's documentation, but not tested on a device yet. Check the map against the manufacturer's documentation before you write to a live device. Tested it? Report a test.

Communication

Protocol
Modbus RTU
Unit ID
1default
Serial
19200 8N1 · 19200 baud, 8 data bits, none parity, 1 stop bit
Byte / word order
ABCD · bytes big-endian, words high first
Addresses
1-based · wire address = address − 1

Connection values are defaults: the device may be configured differently.

Map

Registers
97 holding registers
Groups
7
Translation tables
8
Revision
1 · 2026-10-20
Added
()
File
maps/alfa-instrumentos/3000c.mbmap.json · 21 KB · history
SHA-256
236c68af6989d3f036be2e1cd3a62d7fc66001e0384f08e88b48ad1481530a9c
Manufacturer
alfainstrumentos.com.br

Sources and notes

  • Comandos para Indicadores de Pesagem no Protocolo Modbus-RTU - Linha 3000C / 3000C.S · version 4.3, 2009-08-13
    Section 6.3, commands available in the indicators

Source: Alfa Instrumentos, Comandos para Indicadores de Pesagem no Protocolo Modbus-RTU, Linha 3000C / 3000C.S, revision 4.3

  • Registers are numbered as in the manual, which counts from 1 (address_base 1): register 81 is sent on the wire as address 80. The manual's own examples show this (reading 6 registers from register 81 sends 0 80).
  • Supported functions: 0x03 read, 0x06 write one register, 0x10 write several registers.
  • Each block must be read or written whole: a request that covers only part of a block fails with an exception. The blocks are: 21; write 31 to 39 (9 registers); read 41 to 49 (9); write 51 to 56 (6); read 61 to 66 (6); 71; read 81 to 86 (6); 91; write 101 to 105 (5); read 111 to 115 (5); read 141 to 147 (7); write 161 to 166 (6); read 171 to 177 (7); read 181 and 182 (2); 231; 251; 271; write 851 and 852 (2); read 811 to 819 (9).
  • The level (SetPoint) and clock blocks are written at one address and read at another, so the write registers are marked W and the read registers R. The level write block holds the levels of one bank (HI: levels 4 to 7, LO: levels 0 to 3) chosen in register 31, and all four values must be sent together.
  • Weight, tare and the other 32-bit values are a high register followed by a low one: (register n x 65536) + register n+1, which is the default big word order. The manual gives the sign of the weight as a flag (bit 3 of register 81) and does not state a signed type, so they are read as unsigned. Divide by 10 to the power of the decimal places in bits 0 to 2 of register 81.
  • The 3105 has a different layout of registers 81, 85 and 86 (manual section 6.3.20): bit 7 of register 81 is setup mode, bit 6 compression, bit 5 traction, bit 4 overload or saturation, and registers 85 and 86 hold the compression/traction value instead of the tare. This map follows the layout of section 6.3.7.
  • The manual gives the response of the status block as 12 bytes in section 6.3.7 and 18 bytes in section 6.3.20; six registers are 12 bytes.
  • Registers 231, 251, 271 and 851 are documented for writing only (the response repeats the value sent), so they are marked W. The device address is limited to 0 to 99 when programmed, while the protocol allows 0 to 247.
  • Serial defaults: 19200 baud, 8 data bits, no parity, 2 stop bits. Retries must be at least 100 ms apart.
AreaAddressNameTypeAccessUnitScaleDescription
HR 81 bool bit 6 R
HR 81 bool bit 5 R
HR 81 bool bit 4 R
HR 81 bool bit 3 R
HR 81 uint16 bits 0–2 R Bits 0 to 2: position of the decimal point of the weight and tare
HR 82 bool bit 11 R
HR 82 bool bit 10 R
HR 82 bool bit 9 R
HR 82 bool bit 8 R
HR 82 bool bit 3 R
HR 82 bool bit 2 R
HR 82 bool bit 1 R
HR 82 bool bit 0 R
HR 82 bool bit 6 R
HR 82 bool bit 5 R 0 = net, 1 = gross
HR 82 bool bit 4 R
HR 83 uint32 ABCD R Count shown on the display, with the decimals of register 81
HR 85 uint32 ABCD R Current tare as a count, with the decimals of register 81 (on the 3105 these registers hold the compression/traction value, see notes)
HR 31 uint16 W Write before the level values: bit 6 = store, bits 9 and 10 select the bank
HR 32 uint32 ABCD W Level 1 for the HI bank, level 4 for the LO bank, as the manual names them
HR 34 uint32 ABCD W
HR 36 uint32 ABCD W
HR 38 uint32 ABCD W EMPTY level (VAZIA) or level 7, depending on the bank
HR 41 bool bit 7 R 0 = LO (levels 0 to 3), 1 = HI (levels 4 to 7)
HR 41 uint16 bits 0–5 R Bits 0 to 5
HR 42 uint32 ABCD R
HR 44 uint32 ABCD R
HR 46 uint32 ABCD R
HR 48 uint32 ABCD R
HR 51 uint16 bits 0–6 W % Bits 0 to 6
HR 52 bool bit 0 W 0 = normally open, 1 = normally closed
HR 53 uint16 bits 0–5 W Bits 0 to 5: 3 = levels EMPTY, 1, 2, 3; 4 = levels 0, 1, 2, 3
HR 53 bool bit 6 W 0 = do not store, 1 = store
HR 54 bool bit 0 W 0 = does not latch, 1 = latches
HR 54 bool bit 1 W 0 = does not latch, 1 = latches
HR 55 bool bit 0 W 0 = does not latch, 1 = latches
HR 55 bool bit 1 W 0 = does not latch, 1 = latches
HR 56 bool bit 0 W 0 = does not latch, 1 = latches
HR 56 bool bit 1 W 0 = does not latch, 1 = latches
HR 56 bool bit 2 W 0 = does not latch, 1 = latches
HR 61 uint16 bits 0–6 R % Bits 0 to 6
HR 62 bool bit 0 R 0 = normally open, 1 = normally closed
HR 63 uint16 bits 0–5 R Bits 0 to 5: 3 = levels EMPTY, 1, 2, 3; 4 = levels 0, 1, 2, 3
HR 64 bool bit 0 R 0 = does not latch, 1 = latches
HR 64 bool bit 1 R 0 = does not latch, 1 = latches
HR 65 bool bit 0 R 0 = does not latch, 1 = latches
HR 65 bool bit 1 R 0 = does not latch, 1 = latches
HR 66 bool bit 0 R 0 = does not latch, 1 = latches
HR 66 bool bit 1 R 0 = does not latch, 1 = latches
HR 66 bool bit 2 R 0 = does not latch, 1 = latches
HR 21 uint16 W Write 0 to put the indicator in weight indication mode
HR 71 uint16 W New network address of the indicator, 0 to 99
HR 91 bool bit 0 W Write 1 to run (bit 0 of the remote key register)
HR 91 bool bit 1 W Write 1 to run (bit 1 of the remote key register)
HR 91 bool bit 2 W Write 1 to run (bit 2 of the remote key register)
HR 91 bool bit 3 W Write 1 to run (bit 3 of the remote key register)
HR 91 bool bit 4 W Write 1 to run (bit 4 of the remote key register)
HR 91 bool bit 5 W Write 1 to run (bit 5 of the remote key register)
HR 91 bool bit 6 W Write 1 to run (bit 6 of the remote key register)
HR 231 uint16 bits 0–2 W Bits 0 to 2: zero operating mode
HR 231 bool bit 8 W
HR 251 uint16 W
HR 271 uint16 bits 0–3 W Bits 0 to 3: digital filter type
HR 851 uint32 ABCD W Value used when the tare mode is editable
HR 181 uint32 ABCD R Registers 181 and 182 of the over/under application; the manual marks them as reserved
HR 101 uint16 bits 0–7 W Bits 0 to 7: weight reference
HR 101 bool bit 10 W Bit 10 of register 101: configures A1 / A2
HR 101 bool bit 9 W Bit 9 of register 101: configures P1 / P2
HR 102 uint32 ABCD W
HR 104 uint32 ABCD W
HR 111 uint16 bits 0–7 R Bits 0 to 7
HR 112 uint32 ABCD R
HR 114 uint32 ABCD R
HR 141 uint16 bits 0–2 R Bits 0 to 2
HR 142 uint32 ABCD R
HR 144 uint32 ABCD R
HR 146 uint32 ABCD R
HR 161 uint16 W Write the six registers 161 to 166 together (function 0x10)
HR 162 uint16 W Write the six registers 161 to 166 together (function 0x10)
HR 163 uint16 W Write the six registers 161 to 166 together (function 0x10). Last two digits of the year
HR 164 uint16 W Write the six registers 161 to 166 together (function 0x10)
HR 165 uint16 W Write the six registers 161 to 166 together (function 0x10)
HR 166 uint16 W Write the six registers 161 to 166 together (function 0x10)
HR 171 uint16 R
HR 172 uint16 R
HR 173 uint16 R Last two digits of the year
HR 174 uint16 R
HR 175 uint16 R
HR 176 uint16 R
HR 177 uint16 R
HR 811 uint16 bits 0–2 R Bits 0 to 2: number of decimal places
HR 812 uint16 bits 0–2 R Bits 0 to 2: scale division, 1, 2 or 5
HR 813 uint32 ABCD R PECAL
HR 815 uint32 ABCD R CAPAC, maximum capacity
HR 817 uint16 R
HR 818 uint16 R
HR 819 uint16 R

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