MBMap Registry
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  3. FCR05 / FCR07

BMR FCR05 / FCR07 Modbus register map

Power factor controllers with 5 or 7 outputs (RS485)

  • Official
  • 223 registers
  • Modbus RTU
  • Revision 3 · 2026-11-10
  • Identity: firmware

Official: Written from the manufacturer's documentation, but not tested on a device yet. Check the map against the manufacturer's documentation before you write to a live device. Tested it? Report a test.

Download .mbmap.json Raw JSON View on GitHub Suggest a correction Report a problem

Communication

Protocol
Modbus RTU
Unit ID
1default
Serial
9600 8E1 · 9600 baud, 8 data bits, even parity, 1 stop bit defaults
Byte / word order
ABCD · bytes big-endian, words high first
Addresses
0-based

Connection values are defaults: the device may be configured differently.

Map

Registers
223 holding registers
Groups
10
Translation tables
4
Revision
3 · 2026-11-10
Firmware
from 8.9.5
Added
()
File
maps/bmr/fcr0507.mbmap.json · 36 KB · history
SHA-256
acdc5dc2423a7052665a2547961ecfc1beab29a956e9eb4b4eb63d4390bd1277
Manufacturer
bmr-trading.com

Device identity

What a tool can read to check that this map fits the connected device (SPEC.md section 4.7). Registers with a role are read like any other register.

Registers
RoleRegisterAddressTypeValues
Firmware Firmware version holding 36 float32 ABCD

Sources and notes

  • FCR05/FCR07 Modbus registers · version 1.2

Source: BMR, "FCR05/FCR07 Modbus registers", file version 1.2

  • BMR FCR05 / FCR07 power factor controllers, firmware 8.9.5 and newer.
  • Every register is a float32. The manual gives no function code; this map reads them as holding registers (FC03) and writes them with FC16.
  • Setting values with decimals are sent multiplied by 10 or 100 (a cos phi of 0.80 is sent as 80.0); the scale of each register undoes it.
  • Enumerated settings use codes from 10000: 10001 is Off and 10002 is On.
  • The manual gives no units for the powers, the stage operation counts or the stage on times.
  • The alarm bits assume the low word of Active alarms is the second register, as for big word order.
AreaAddressNameTypeAccessUnitScaleDescription
HR 20 uint16 R
HR 21 uint16 R Status bits of the stage
HR 22 uint16 R Status bits of the stage
HR 23 uint16 R Status bits of the stage
HR 24 uint16 R Status bits of the stage
HR 25 uint16 R Status bits of the stage
HR 26 uint16 R Status bits of the stage
HR 27 uint16 R Status bits of the stage
HR 28 uint16 R Status bits of the stage
HR 29 uint16 R Status bits of the stage
HR 30 uint16 R Status bits of the stage
HR 31 uint16 R Status bits of the stage
HR 32 uint16 R Status bits of the stage
HR 33 uint16 R s
HR 34 int16 R °C
HR 36 float32 ABCD R
HR 50 float32 ABCD R
HR 52 float32 ABCD R
HR 54 float32 ABCD R
HR 56 float32 ABCD R
HR 58 float32 ABCD R
HR 60 float32 ABCD R A
HR 62 float32 ABCD R %
HR 64 float32 ABCD R %
HR 66 float32 ABCD R %
HR 68 float32 ABCD R %
HR 70 float32 ABCD R %
HR 72 float32 ABCD R %
HR 74 float32 ABCD R %
HR 76 float32 ABCD R %
HR 78 float32 ABCD R %
HR 80 float32 ABCD R %
HR 82 float32 ABCD R V
HR 84 float32 ABCD R %
HR 86 float32 ABCD R %
HR 88 float32 ABCD R %
HR 90 float32 ABCD R %
HR 92 float32 ABCD R %
HR 94 float32 ABCD R %
HR 96 float32 ABCD R %
HR 98 float32 ABCD R %
HR 100 float32 ABCD R %
HR 102 float32 ABCD R %
HR 104 float32 ABCD R
HR 106 float32 ABCD R
HR 108 float32 ABCD R
HR 110 float32 ABCD R
HR 112 float32 ABCD R
HR 114 float32 ABCD R
HR 116 float32 ABCD R
HR 118 float32 ABCD R
HR 120 float32 ABCD R
HR 122 float32 ABCD R
HR 124 float32 ABCD R
HR 136 float32 ABCD R
HR 138 float32 ABCD R
HR 140 float32 ABCD R
HR 142 float32 ABCD R
HR 144 float32 ABCD R
HR 146 float32 ABCD R
HR 148 float32 ABCD R
HR 160 float32 ABCD R Hz
HR 162 float32 ABCD R A
HR 164 float32 ABCD R %
HR 166 float32 ABCD R %
HR 168 float32 ABCD R %
HR 170 float32 ABCD R %
HR 172 float32 ABCD R %
HR 174 float32 ABCD R %
HR 176 float32 ABCD R %
HR 178 float32 ABCD R %
HR 180 float32 ABCD R %
HR 182 float32 ABCD R %
HR 184 float32 ABCD R V
HR 186 float32 ABCD R %
HR 188 float32 ABCD R %
HR 190 float32 ABCD R %
HR 192 float32 ABCD R %
HR 194 float32 ABCD R %
HR 196 float32 ABCD R %
HR 198 float32 ABCD R %
HR 200 float32 ABCD R %
HR 202 float32 ABCD R %
HR 204 float32 ABCD R %
HR 206 float32 ABCD R
HR 208 float32 ABCD R
HR 210 float32 ABCD R
HR 212 float32 ABCD R
HR 214 float32 ABCD R Hz
HR 216 float32 ABCD R Hz
HR 218 float32 ABCD R °C
HR 226 float32 ABCD R V
HR 228 float32 ABCD R V
HR 230 float32 ABCD R A
HR 232 float32 ABCD R A
HR 234 float32 ABCD R
HR 236 float32 ABCD R %
HR 238 float32 ABCD R %
HR 240 float32 ABCD R °C
HR 242 uint32 ABCD R One bit per stage with the stage operations alarm: bit 0 = stage 1

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