MBMap Registry
  1. Devices
  2. Klemsan
  3. RAPIDUS

Klemsan RAPIDUS Modbus register map

3-phase reactive power controller (capacitor bank), Modbus RTU. All registers 32-bit (stride +2). Common data 0-26 (avg V/I, total P/Q/S, avg cosΦ/PF, L-L voltages 1-2/2-3/3-1/avg, neutral I, total THDV/THDI, f32 RO). Per-phase data 28-150 / 152-274 / 276-398: basic (V,I,P,Q,S,cosΦ,PF,freq,THDV,THDI f32) + V harmonics 1,3,...,51 and I harmonics 1,3,...,51 (all f32 RO). Alarm flags at 400 (first 32bits) and 402 (second 32bits, u32 RO). Step variables 404-456: active/available/fixed step flags + switching counts + operation times (u32 RO) for 12 capacitor steps. Tariff meters 458-512 (active/reactive import/export kWh/kVArh, current/last hour/day/month, f32 RO). Demand 514-576 (total+per-phase P/Q/S/I demand values + timestamps, f32/u32 RO). Other 578-582: temperature/battery/time. Alarm log 584-982: 50 events (4 registers each: timestamp u32, ID u32, state u32, value f32). History file numbers 984-988. Step estimated powers 990-1012 (DCM option, f32). Config 2000-2312: network (CTR/VTR/demand period), energy tariff T1 counters, bank (12 steps power/type, bank power/count/discharge), compensation (steps/program/targets/timing/angle), comms (baud/slave), alarm limits for V-LN/V-LL/I/P/Q/S/IN/PF/cosΦ/freq/temp/V-harmonics/I-harmonics/inductive+capacitive energy, auxiliary, learn, device (language/contrast/password/display/serial). Clear commands 1898-1916 (WO). Save 1998 (WO, write 1 to commit config to flash).

  • Unofficial
  • 486 registers
  • Revision 2

Unofficial: Copied from an unofficial source and not tested. Read it as a draft and check a value on the real device before you rely on the rest. Check the map against the manufacturer's documentation before you write to a live device. Tested it? Report a test.

Download .mbmap.json Raw JSON View on GitHub Suggest a correction Report a problem

Communication

Protocol
Modbus TCP and RTUdefault
Unit ID
1default
TCP port
502default
Serial
9600 8E1 · 9600 baud, 8 data bits, even parity, 1 stop bit defaults
Byte / word order
ABCD · bytes big-endian, words high first
Addresses
0-based

Connection values are defaults: the device may be configured differently.

Map

Registers
486 holding registers
Revision
2
Added
()
File
maps/klemsan/rapidus.mbmap.json · 56 KB · history
SHA-256
c67033d161f46e60feda5a6803bb9643bcd0e638fe231f19f089cb34b4911062
Manufacturer
klemsan.ir

Sources and notes

Source: Omni Console device library (OmniCoreST), modbus-library/klemsan-rapidus.toml; Source: klemsan-rapidus-modbus-kullanim-kilavuzu-tr.pdf (30 pages). Not verified against the manufacturer's documentation

  • Klemsan RAPIDUS.
  • Converted automatically from the Omni Console device library (OmniCoreST).
  • Not verified against the manufacturer's documentation.
  • Corrections are welcome (CONTRIBUTING.md). Change x_status once this table has been checked against the manual.
  • | Klemsan RAPIDUS Reactive Power Controller — Modbus RTU Register Map
  • |
  • | Source: klemsan-rapidus-modbus-kullanim-kilavuzu-tr.pdf (30 pages)
  • | Product: RAPIDUS — automatic reactive power controller / capacitor bank controller
  • | Protocol: Modbus RTU
  • | FC03 (0x03) — Read Holding Registers (read all parameters)
  • | FC06 (0x06) — Write Single Register
  • | FC10 (0x10) — Write Multiple Registers (write config + clear commands)
  • | FC14 (0x14) — Read File Record (history archive; file numbers in registers 984/986/988)
  • | Data types: 32-bit registers (all stride +2); f32 = IEEE 754 float; u32 = 32-bit signed int
  • | (Rapidus calls it "int = 32-bit işaretli tam sayı, little-endian b0,b1,b2,b3")
  • | Unix timestamps stored as u32 (seconds since epoch).
  • | Save config changes: write 1 to register 1998 within 60 s of last write.
  • | History archive (FC14): hourly files 1-1920, daily 5001-5240, monthly 10001-10036.
AreaAddressNameTypeAccessUnitScaleDescription
HR 0 float32 ABCD R
HR 2 float32 ABCD R
HR 4 float32 ABCD R
HR 6 float32 ABCD R
HR 8 float32 ABCD R
HR 10 float32 ABCD R
HR 12 float32 ABCD R
HR 14 float32 ABCD R
HR 16 float32 ABCD R
HR 18 float32 ABCD R
HR 20 float32 ABCD R
HR 22 float32 ABCD R
HR 24 float32 ABCD R
HR 26 float32 ABCD R
HR 28 float32 ABCD R
HR 30 float32 ABCD R
HR 32 float32 ABCD R
HR 34 float32 ABCD R
HR 36 float32 ABCD R
HR 38 float32 ABCD R
HR 40 float32 ABCD R
HR 42 float32 ABCD R
HR 44 float32 ABCD R
HR 46 float32 ABCD R
HR 48 float32 ABCD R
HR 50 float32 ABCD R
HR 52 float32 ABCD R
HR 54 float32 ABCD R
HR 56 float32 ABCD R
HR 58 float32 ABCD R
HR 60 float32 ABCD R
HR 62 float32 ABCD R
HR 64 float32 ABCD R
HR 66 float32 ABCD R
HR 68 float32 ABCD R
HR 70 float32 ABCD R
HR 72 float32 ABCD R
HR 74 float32 ABCD R
HR 76 float32 ABCD R
HR 78 float32 ABCD R
HR 80 float32 ABCD R
HR 82 float32 ABCD R
HR 84 float32 ABCD R
HR 86 float32 ABCD R
HR 88 float32 ABCD R
HR 90 float32 ABCD R
HR 92 float32 ABCD R
HR 94 float32 ABCD R
HR 96 float32 ABCD R
HR 98 float32 ABCD R
HR 100 float32 ABCD R
HR 102 float32 ABCD R
HR 104 float32 ABCD R
HR 106 float32 ABCD R
HR 108 float32 ABCD R
HR 110 float32 ABCD R
HR 112 float32 ABCD R
HR 114 float32 ABCD R
HR 116 float32 ABCD R
HR 118 float32 ABCD R
HR 120 float32 ABCD R
HR 122 float32 ABCD R
HR 124 float32 ABCD R
HR 126 float32 ABCD R
HR 128 float32 ABCD R
HR 130 float32 ABCD R
HR 132 float32 ABCD R
HR 134 float32 ABCD R
HR 136 float32 ABCD R
HR 138 float32 ABCD R
HR 140 float32 ABCD R
HR 142 float32 ABCD R
HR 144 float32 ABCD R
HR 146 float32 ABCD R
HR 148 float32 ABCD R
HR 150 float32 ABCD R
HR 152 float32 ABCD R
HR 154 float32 ABCD R
HR 156 float32 ABCD R
HR 158 float32 ABCD R
HR 160 float32 ABCD R
HR 162 float32 ABCD R
HR 164 float32 ABCD R
HR 166 float32 ABCD R
HR 168 float32 ABCD R
HR 170 float32 ABCD R
HR 172 float32 ABCD R
HR 174 float32 ABCD R
HR 176 float32 ABCD R
HR 178 float32 ABCD R
HR 180 float32 ABCD R
HR 182 float32 ABCD R
HR 184 float32 ABCD R
HR 186 float32 ABCD R
HR 188 float32 ABCD R
HR 190 float32 ABCD R
HR 192 float32 ABCD R
HR 194 float32 ABCD R
HR 196 float32 ABCD R
HR 198 float32 ABCD R

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