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  3. UMG 96-PA

Janitza UMG 96-PA Modbus register map

Also covers UMG 96-PA-MID+

96 mm panel power analyser with RS-485 (Modbus RTU), Ethernet through an optional module

  • Official
  • 61 registers
  • Modbus TCP and RTU
  • Revision 2 · 2026-10-17

Official: Written from the manufacturer's documentation, but not tested on a device yet. Check the map against the manufacturer's documentation before you write to a live device. Tested it? Report a test.

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Communication

Protocol
Modbus TCP and RTU
Unit ID
1
TCP port
502
Serial
9600 8E1 · 9600 baud, 8 data bits, even parity, 1 stop bit
Byte / word order
ABCD · bytes big-endian, words high first
Addresses
0-based

Connection values are defaults: the device may be configured differently.

Map

Registers
61 holding registers
Groups
1
Revision
2 · 2026-10-17
Firmware
from firmware 3.10, hardware index 1
Added
()
File
maps/janitza/umg-96-pa.mbmap.json · 12 KB · history
SHA-256
09546c560ac51c38417a95bb69e1f3a01a3c72921243a4b7cfb7315a6884358a
Manufacturer
janitza.com

Sources and notes

Source: Janitza electronics, "UMG 96-PA / UMG 96-PA-MID+ User manual and technical data", Doc. no. 2.061.059.3.d (2021-09)

  • Addresses are the protocol addresses of the address list; all values are holding registers (FC03 read, FC06/FC16 write).
  • The baud rate is set on the device (default Auto; 9600 to 115200) and the data frame to odd, even or no parity.
  • Not in this map: the full Modbus address list, which Janitza publishes separately; this map covers the frequently used measured values in section 18.2 of the user manual.
AreaAddressNameTypeAccessUnitScaleDescription
HR 19000 float32 ABCD R V _ULN[0]
HR 19002 float32 ABCD R V _ULN[1]
HR 19004 float32 ABCD R V _ULN[2]
HR 19006 float32 ABCD R V _ULL[0]
HR 19008 float32 ABCD R V _ULL[1]
HR 19010 float32 ABCD R V _ULL[2]
HR 19012 float32 ABCD R A _ILN[0]
HR 19014 float32 ABCD R A _ILN[1]
HR 19016 float32 ABCD R A _ILN[2]
HR 19018 float32 ABCD R A _I_SUM3
HR 19020 float32 ABCD R W _PLN[0]
HR 19022 float32 ABCD R W _PLN[1]
HR 19024 float32 ABCD R W _PLN[2]
HR 19026 float32 ABCD R W _P_SUM3
HR 19028 float32 ABCD R VA _SLN[0]
HR 19030 float32 ABCD R VA _SLN[1]
HR 19032 float32 ABCD R VA _SLN[2]
HR 19034 float32 ABCD R VA _S_SUM3
HR 19036 float32 ABCD R var _QLN[0]
HR 19038 float32 ABCD R var _QLN[1]
HR 19040 float32 ABCD R var _QLN[2]
HR 19042 float32 ABCD R var _Q_SUM3
HR 19044 float32 ABCD R _COS_PHI[0]
HR 19046 float32 ABCD R _COS_PHI[1]
HR 19048 float32 ABCD R _COS_PHI[2]
HR 19050 float32 ABCD R Hz _FREQ
HR 19052 float32 ABCD R _PHASE_SEQ
HR 19054 float32 ABCD R Wh _WH_V[0]
HR 19056 float32 ABCD R Wh _WH_V[1]
HR 19058 float32 ABCD R Wh _WH_V[2]
HR 19060 float32 ABCD R Wh _WH_V_HT_SUML13
HR 19062 float32 ABCD R Wh _WH_V[0]
HR 19064 float32 ABCD R Wh _WH_V[1]
HR 19066 float32 ABCD R Wh _WH_V[2]
HR 19068 float32 ABCD R Wh _WH_V_HT_SUML13
HR 19070 float32 ABCD R Wh _WH_Z[0]
HR 19072 float32 ABCD R Wh _WH_Z[1]
HR 19074 float32 ABCD R Wh _WH_Z[2]
HR 19076 float32 ABCD R Wh _WH_Z_SUML13
HR 19078 float32 ABCD R VAh _WH_S[0]
HR 19080 float32 ABCD R VAh _WH_S[1]
HR 19082 float32 ABCD R VAh _WH_S[2]
HR 19084 float32 ABCD R VAh _WH_S_SUML13
HR 19086 float32 ABCD R varh _IQH[0]
HR 19088 float32 ABCD R varh _IQH[1]
HR 19090 float32 ABCD R varh _IQH[2]
HR 19092 float32 ABCD R varh _IQH_SUML13
HR 19094 float32 ABCD R varh _IQH[0]
HR 19096 float32 ABCD R varh _IQH[1]
HR 19098 float32 ABCD R varh _IQH[2]
HR 19100 float32 ABCD R varh _IQH_SUML13
HR 19102 float32 ABCD R varh _CQH[0]
HR 19104 float32 ABCD R varh _CQH[1]
HR 19106 float32 ABCD R varh _CQH[2]
HR 19108 float32 ABCD R varh _CQH_SUML13
HR 19110 float32 ABCD R % _THD_ULN[0]
HR 19112 float32 ABCD R % _THD_ULN[1]
HR 19114 float32 ABCD R % _THD_ULN[2]
HR 19116 float32 ABCD R % _THD_ILN[0]
HR 19118 float32 ABCD R % _THD_ILN[1]
HR 19120 float32 ABCD R % _THD_ILN[2]

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