Janitza UMG104 Modbus register map

Also covers UMG 104

Power analyser for DIN rail mounting, RS-485 (Modbus RTU) and RS-232

Official
283 registers
Modbus RTU
Revision 2 · 2026-10-17
Identity: serial number

Official: Written from the manufacturer's documentation, but not tested on a device yet. Check the map against the manufacturer's documentation before you write to a live device. Tested it? Report a test.

Download .mbmap.json Raw JSON View on GitHub Suggest a correction Report a problem

Communication

Protocol: Modbus RTU
Unit ID: 1
Serial: 9600 8N2 · 9600 baud, 8 data bits, none parity, 2 stop bits
Byte / word order: ABCD · bytes big-endian, words high first
Addresses: 0-based

Connection values are defaults: the device may be configured differently.

Map

Registers: 283 holding registers
Groups: 4
Revision: 2 · 2026-10-17
Firmware: 1.268
Added: 2026-10-14 (2026-10-14)
File: maps/janitza/umg104.mbmap.json · 51 KB · history
SHA-256: 1b4493f4979a13a8801ca2901c02471747ad5963bb45a4846a04f9c04ef84985
Manufacturer: janitza.com

Device identity

What a tool can read to check that this map fits the connected device (SPEC.md section 4.7). Registers with a role are read like any other register.

Registers
Role	Register	Address	Type	Values
Serial number	Serial number	holding 10176	uint32 ABCD

Sources and notes

Power Analyser UMG 104 Modbus-address list and Formulary · version Doc. no. 1.041.006.1.e, 2023-01
frequently required readings, date and time, energy and other values

Source: Janitza electronics, "Power Analyser UMG 104 Modbus-address list and Formulary", Doc. no. 1.041.006.1.e (2023-01)

Addresses are the protocol addresses of the address list; all values are holding registers (FC03 read, FC06/FC16 write).
Values are big-endian; the device also serves them little-endian at the same address + 32768.
Not in this map: the 200 ms, mean, minimum and maximum value tables, their time stamps and the Fourier analysis tables.
Serial settings: 8 data bits, no parity, 2 stop bits; 9600 to 115200 baud.

Area	Address	Type	Access	Unit	Description
HR	19000	float32 ABCD	R	V	_ULN[0]
HR	19002	float32 ABCD	R	V	_ULN[1]
HR	19004	float32 ABCD	R	V	_ULN[2]
HR	19006	float32 ABCD	R	V	_ULL[0]
HR	19008	float32 ABCD	R	V	_ULL[1]
HR	19010	float32 ABCD	R	V	_ULL[2]
HR	19012	float32 ABCD	R	A	_ILN[0]
HR	19014	float32 ABCD	R	A	_ILN[1]
HR	19016	float32 ABCD	R	A	_ILN[2]
HR	19018	float32 ABCD	R	A	_I_SUM3
HR	19020	float32 ABCD	R	W	_PLN[0]
HR	19022	float32 ABCD	R	W	_PLN[1]
HR	19024	float32 ABCD	R	W	_PLN[2]
HR	19026	float32 ABCD	R	W	_P_SUM3
HR	19028	float32 ABCD	R	VA	_SLN[0]
HR	19030	float32 ABCD	R	VA	_SLN[1]
HR	19032	float32 ABCD	R	VA	_SLN[2]
HR	19034	float32 ABCD	R	VA	_S_SUM3
HR	19036	float32 ABCD	R	var	_QLN[0]
HR	19038	float32 ABCD	R	var	_QLN[1]
HR	19040	float32 ABCD	R	var	_QLN[2]
HR	19042	float32 ABCD	R	var	_Q_SUM3
HR	19044	float32 ABCD	R		_COS_PHI[0]
HR	19046	float32 ABCD	R		_COS_PHI[1]
HR	19048	float32 ABCD	R		_COS_PHI[2]
HR	19050	float32 ABCD	R	Hz	_FREQ
HR	19052	float32 ABCD	R		_PHASE_SEQ
HR	19054	float32 ABCD	R	Wh	_WH[0]
HR	19056	float32 ABCD	R	Wh	_WH[1]
HR	19058	float32 ABCD	R	Wh	_WH[2]
HR	19060	float32 ABCD	R	Wh	_WH_SUML13
HR	19062	float32 ABCD	R	Wh	_WH_V[0]
HR	19064	float32 ABCD	R	Wh	_WH_V[1]
HR	19066	float32 ABCD	R	Wh	_WH_V[2]
HR	19068	float32 ABCD	R	Wh	_WH_V_HT_SUML13
HR	19070	float32 ABCD	R	Wh	_WH_Z[0]
HR	19072	float32 ABCD	R	Wh	_WH_Z[1]
HR	19074	float32 ABCD	R	Wh	_WH_Z[2]
HR	19076	float32 ABCD	R	Wh	_WH_Z_SUML13
HR	19078	float32 ABCD	R	VAh	_WH_S[0]
HR	19080	float32 ABCD	R	VAh	_WH_S[1]
HR	19082	float32 ABCD	R	VAh	_WH_S[2]
HR	19084	float32 ABCD	R	VAh	_WH_S_SUML13
HR	19086	float32 ABCD	R	varh	_QH[0]
HR	19088	float32 ABCD	R	varh	_QH[1]
HR	19090	float32 ABCD	R	varh	_QH[2]
HR	19092	float32 ABCD	R	varh	_QH_SUML13
HR	19094	float32 ABCD	R	varh	_IQH[0]
HR	19096	float32 ABCD	R	varh	_IQH[1]
HR	19098	float32 ABCD	R	varh	_IQH[2]
HR	19100	float32 ABCD	R	varh	_IQH_SUML13
HR	19102	float32 ABCD	R	varh	_CQH[0]
HR	19104	float32 ABCD	R	varh	_CQH[1]
HR	19106	float32 ABCD	R	varh	_CQH[2]
HR	19108	float32 ABCD	R	varh	_CQH_SUML13
HR	19110	float32 ABCD	R	%	_THD_ULN[0]
HR	19112	float32 ABCD	R	%	_THD_ULN[1]
HR	19114	float32 ABCD	R	%	_THD_ULN[2]
HR	19116	float32 ABCD	R	%	_THD_ILN[0]
HR	19118	float32 ABCD	R	%	_THD_ILN[1]
HR	19120	float32 ABCD	R	%	_THD_ILN[2]
HR	0	int64 ABCD	R		_REALTIME
HR	4	int32 ABCD	R	s	_SYSTIME
HR	6	int16	R		_DAY
HR	8	int16	R		_YEAR
HR	9	int16	R	h	_HOUR
HR	10	int16	R	min	_MIN
HR	11	int16	R	s	_SEC
HR	12	int16	R		_WEEKDAY
HR	9971	float32 ABCD	R	V	_SPU012
HR	9973	int16	RW		_DIGOUT_STAT[0]
HR	9974	int16	RW		_DIGOUT_STAT[1]
HR	9975	int16	R		_DIGIN_STAT[0]
HR	9976	int16	R		_DIGIN_STAT[1]
HR	9985	uint32 ABCD	RW		_RX232_COUNT
HR	9987	uint32 ABCD	RW		_TX232_COUNT
HR	9989	uint32 ABCD	RW		_ERR232_COUNT
HR	9991	uint32 ABCD	RW		_RX485_COUNT
HR	9993	uint32 ABCD	RW		_TX485_COUNT
HR	9995	uint32 ABCD	RW		_ERR485_COUNT
HR	10032	float32 ABCD	RW	A	_CTPRIM[0]
HR	10034	float32 ABCD	RW	A	_CTPRIM[1]
HR	10036	float32 ABCD	RW	A	_CTPRIM[2]
HR	10038	float32 ABCD	RW	A	_CTPRIM[3]
HR	10040	float32 ABCD	RW	A	_CTSEC[0]
HR	10042	float32 ABCD	RW	A	_CTSEC[1]
HR	10044	float32 ABCD	RW	A	_CTSEC[2]
HR	10046	float32 ABCD	RW	A	_CTSEC[3]
HR	10048	float32 ABCD	RW	V	_VTPRIM[0]
HR	10050	float32 ABCD	RW	V	_VTPRIM[1]
HR	10052	float32 ABCD	RW	V	_VTPRIM[2]
HR	10054	float32 ABCD	RW	V	_VTPRIM[3]
HR	10056	float32 ABCD	RW	V	_VTSEC[0]
HR	10058	float32 ABCD	RW	V	_VTSEC[1]
HR	10060	float32 ABCD	RW	V	_VTSEC[2]
HR	10062	float32 ABCD	RW	V	_VTSEC[3]
HR	10064	float32 ABCD	RW	A	_IRATED[0]
HR	10066	float32 ABCD	RW	A	_IRATED[1]
HR	10068	float32 ABCD	RW	A	_IRATED[2]
HR	10070	float32 ABCD	RW	A	_IRATED[3]

Help improve this map

I tested it on a deviceReport whether it worked, even if you did not write the map.
Suggest a correctionEdit the file on GitHub; it opens a pull request.
Report a problemA wrong address, type, scale or byte order.
Read the formatWhat each key of the file means (SPEC.md).