Moxa ioLogik E2214 Modbus register map
Also covers ioLogik E2214-T
Ethernet micro controller with 6 digital inputs and 6 relay outputs (Click&Go logic)
- Official
- 300 registers
- Modbus TCP
- Revision 2 · 2026-10-17
Official: Written from the manufacturer's documentation, but not tested on a device yet. Check the map against the manufacturer's documentation before you write to a live device. Tested it? Report a test.
Communication
- Protocol
- Modbus TCP
- Unit ID
- 1
- TCP port
- 502
- Byte / word order
- ABCD · bytes big-endian, words high first
- Addresses
- 0-based
Connection values are defaults: the device may be configured differently.
Map
- Registers
- 174 holding registers, 48 input registers, 72 coils, 6 discrete inputs
- Groups
- 3
- Revision
- 2 · 2026-10-17
- Added
- ()
- File
- maps/moxa/iologik-e2214.mbmap.json · 49 KB · history
- SHA-256
- 2678067159a41ae1e22062a8829df400e1cb8f86d15540bd4679cc4faae7cb4d
- Manufacturer
- moxa.com
Sources and notes
- ioLogik E2200 Series User Manual · version 7.2, 2022-07 Appendix I, ioLogik E2214 Modbus mapping
Source: Moxa, "ioLogik E2200 Series User Manual", version 7.2 (July 2022), Appendix I
- Modbus/TCP address map from Appendix I of the manual. Many values appear twice, as a coil or discrete input and again as a holding register (names ending in "(register)").
- 32-bit values are two registers; the manual lists the high word first unless the register says otherwise.
- Not in this map: the DI counter mode values at holding 0x0D00, which the manual lists as two-word values at consecutive addresses.
| Area | Address | Name | Type | Access | Unit | Scale | Description |
|---|---|---|---|---|---|---|---|
| CO | 0 | bool | RW | ||||
| CO | 1 | bool | RW | ||||
| CO | 2 | bool | RW | ||||
| CO | 3 | bool | RW | ||||
| CO | 4 | bool | RW | ||||
| CO | 5 | bool | RW | ||||
| CO | 6 | bool | RW | ||||
| CO | 7 | bool | RW | ||||
| CO | 8 | bool | RW | ||||
| CO | 9 | bool | RW | ||||
| CO | 10 | bool | RW | ||||
| CO | 11 | bool | RW | ||||
| CO | 12 | bool | RW | ||||
| CO | 13 | bool | RW | ||||
| CO | 14 | bool | RW | ||||
| CO | 15 | bool | RW | ||||
| CO | 16 | bool | RW | ||||
| CO | 17 | bool | RW | ||||
| CO | 18 | bool | RW | ||||
| CO | 19 | bool | RW | ||||
| CO | 20 | bool | RW | ||||
| CO | 21 | bool | RW | ||||
| CO | 22 | bool | RW | ||||
| CO | 23 | bool | RW | ||||
| CO | 24 | bool | RW | ||||
| CO | 25 | bool | RW | ||||
| CO | 26 | bool | RW | ||||
| CO | 27 | bool | RW | ||||
| CO | 28 | bool | RW | ||||
| CO | 29 | bool | RW | ||||
| CO | 30 | bool | RW | ||||
| CO | 31 | bool | RW | ||||
| CO | 32 | bool | RW | ||||
| CO | 33 | bool | RW | ||||
| CO | 34 | bool | RW | ||||
| CO | 35 | bool | RW | ||||
| CO | 36 | bool | RW | Read aways :0 Write: 1 : Clear counter value 0 : return Illegal Data Value | |||
| CO | 37 | bool | RW | Read aways :0 Write: 1 : Clear counter value 0 : return Illegal Data Value | |||
| CO | 38 | bool | RW | Read aways :0 Write: 1 : Clear counter value 0 : return Illegal Data Value | |||
| CO | 39 | bool | RW | Read aways :0 Write: 1 : Clear counter value 0 : return Illegal Data Value | |||
| CO | 40 | bool | RW | Read aways :0 Write: 1 : Clear counter value 0 : return Illegal Data Value | |||
| CO | 41 | bool | RW | Read aways :0 Write: 1 : Clear counter value 0 : return Illegal Data Value | |||
| CO | 42 | bool | RW | Read: 0 : Normal 1 : Overflow Write: 0 : clear overflow status 1 : return Illegal Data Value | |||
| CO | 43 | bool | RW | Read: 0 : Normal 1 : Overflow Write: 0 : clear overflow status 1 : return Illegal Data Value | |||
| CO | 44 | bool | RW | Read: 0 : Normal 1 : Overflow Write: 0 : clear overflow status 1 : return Illegal Data Value | |||
| CO | 45 | bool | RW | Read: 0 : Normal 1 : Overflow Write: 0 : clear overflow status 1 : return Illegal Data Value | |||
| CO | 46 | bool | RW | Read: 0 : Normal 1 : Overflow Write: 0 : clear overflow status 1 : return Illegal Data Value | |||
| CO | 47 | bool | RW | Read: 0 : Normal 1 : Overflow Write: 0 : clear overflow status 1 : return Illegal Data Value | |||
| CO | 48 | bool | RW | ||||
| CO | 49 | bool | RW | ||||
| CO | 50 | bool | RW | ||||
| CO | 51 | bool | RW | ||||
| CO | 52 | bool | RW | ||||
| CO | 53 | bool | RW | ||||
| CO | 54 | bool | RW | ||||
| CO | 55 | bool | RW | ||||
| CO | 56 | bool | RW | ||||
| CO | 57 | bool | RW | ||||
| CO | 58 | bool | RW | ||||
| CO | 59 | bool | RW | ||||
| CO | 60 | bool | RW | ||||
| CO | 61 | bool | RW | ||||
| CO | 62 | bool | RW | ||||
| CO | 63 | bool | RW | ||||
| CO | 64 | bool | RW | ||||
| CO | 65 | bool | RW | ||||
| CO | 66 | bool | RW | ||||
| CO | 67 | bool | RW | ||||
| CO | 68 | bool | RW | ||||
| CO | 69 | bool | RW | ||||
| CO | 70 | bool | RW | ||||
| CO | 71 | bool | RW | ||||
| DI | 0 | bool | R | ||||
| DI | 1 | bool | R | ||||
| DI | 2 | bool | R | ||||
| DI | 3 | bool | R | ||||
| DI | 4 | bool | R | ||||
| DI | 5 | bool | R | ||||
| IR | 0 | uint32 ABCD | R | ||||
| IR | 2 | uint32 ABCD | R | ||||
| IR | 4 | uint32 ABCD | R | ||||
| IR | 6 | uint32 ABCD | R | ||||
| IR | 8 | uint32 ABCD | R | ||||
| IR | 10 | uint32 ABCD | R | ||||
| IR | 12 | uint32 ABCD | R | ||||
| IR | 14 | uint32 ABCD | R | ||||
| IR | 16 | uint32 ABCD | R | ||||
| IR | 18 | uint32 ABCD | R | ||||
| IR | 20 | uint32 ABCD | R | ||||
| IR | 22 | uint32 ABCD | R | ||||
| IR | 24 | uint16 | R | ||||
| IR | 25 | uint16 | R | ||||
| IR | 26 | uint16 | R | ||||
| IR | 27 | uint16 | R | ||||
| IR | 28 | uint16 | R | ||||
| IR | 29 | uint16 | R | ||||
| IR | 30 | uint16 | R | ||||
| IR | 31 | uint16 | R | ||||
| IR | 32 | uint16 | R | ||||
| IR | 33 | uint16 | R |
No registers match
Try part of the name, an address (decimal or 0x hex) or clear the filters.
Help improve this map
- I tested it on a deviceReport whether it worked, even if you did not write the map.
- Suggest a correctionEdit the file on GitHub; it opens a pull request.
- Report a problemA wrong address, type, scale or byte order.
- Read the formatWhat each key of the file means (SPEC.md).