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  3. ioThinx 45MR-2606

Moxa ioThinx 45MR-2606 Modbus register map

Also covers ioThinx 45MR-2606-T

8 digital input and 8 digital output module for the ioThinx 4510 adapter

  • Official
  • 56 registers
  • Modbus TCP
  • Revision 3 · 2026-11-11

Official: Written from the manufacturer's documentation, but not tested on a device yet. Check the map against the manufacturer's documentation before you write to a live device. Tested it? Report a test.

Communication

Protocol
Modbus TCP
Unit ID
1
TCP port
502
Byte / word order
ABCD · bytes big-endian, words high first
Addresses
0-based

Connection values are defaults: the device may be configured differently.

Map

Registers
12 holding registers, 4 input registers, 14 coils, 26 discrete inputs
Groups
20
Revision
3 · 2026-11-11
Added
()
File
maps/moxa/iothinx-45mr-2606.mbmap.json · 12 KB · history
SHA-256
f357ee0483312451d4922a4369a45c8dff90a13a3d8d5a4d23f17e6e88f1fa32
Manufacturer
moxa.com

Sources and notes

  • ioThinx 4510 Series User's Manual · version 6.2, 2024-07
    Appendix A, 45MR-2606 (-T) registers

Source: Moxa, ioThinx 4510 Series User's Manual, version 6.2 (July 2024), Appendix A (Modbus/TCP slave rules and register lists)

  • Addresses are relative to the module: the Modbus address on the 4510 is the slot's base address (set on the Modbus page of the 4510 web console: reload the default addresses or edit them) plus the relative address given here, separately for coils, discrete inputs, holding registers and input registers. Modbus/TCP port 502 on the ioThinx 4510 adapter.
  • The manual lists every parameter with a length: in bits for coils and discrete inputs, and in 16-bit registers for the others. A DWORD or REAL value takes two registers; a REAL is a 32-bit float. Per-channel entries here follow that: for example 8 registers of DWORD for 4 channels are four 32-bit values.
  • The manual does not state the word order of the 32-bit values; big is assumed. The function codes are 1, 5 and 15 for coils, 2 for discrete inputs, 3, 6 and 16 for holding registers and 4 for input registers.
  • Each 'All' register is a bit mask with one bit per channel.
  • The earlier version of this map read the counters as 64-bit values; the manual and its RESTful API list them as 32-bit (0 to 4294967295).
AreaAddressNameTypeAccessUnitScaleDescription
CO 0 bool RW DO - status (0: OFF, 1: ON)
CO 1 bool RW
CO 2 bool RW
CO 3 bool RW
CO 4 bool RW
CO 5 bool RW
CO 6 bool RW
CO 7 bool RW
CO 8 bool RW DI - Counter mode - status (0: Pause, 1: Run)
CO 9 bool RW
CO 10 bool RW DI - Counter mode - clear overflow flag (1: Clear)
CO 11 bool RW
CO 12 bool RW DO - Pulse mode - status (0: Stop, 1: Start)
CO 13 bool RW
DI 0 bool R DI - DI mode - status (0: OFF, 1: ON)
DI 1 bool R
DI 2 bool R
DI 3 bool R
DI 4 bool R
DI 5 bool R
DI 6 bool R
DI 7 bool R
DI 8 bool R DI - mode (0: DI, 1: Counter)
DI 9 bool R
DI 10 bool R
DI 11 bool R
DI 12 bool R
DI 13 bool R
DI 14 bool R
DI 15 bool R
DI 16 bool R DO - mode (0: DO, 1: Pulse)
DI 17 bool R
DI 18 bool R
DI 19 bool R
DI 20 bool R
DI 21 bool R
DI 22 bool R
DI 23 bool R
DI 24 bool R DI - Counter mode - overflow flag (0: Normal, 1:
DI 25 bool R
HR 0 uint32 ABCD RW DI - Counter mode - value
HR 2 uint32 ABCD RW
HR 4 uint16 RW DO - status (0: OFF, 1: ON); bit n is channel n
HR 5 uint32 ABCD RW DO - Pulse mode - count
HR 7 uint32 ABCD RW
HR 9 uint16 RW µs ×500 DO - Pulse mode - ON width (unit: 500 us)
HR 10 uint16 RW µs ×500
HR 11 uint16 RW µs ×500 DO - Pulse mode - OFF width (unit: 500 us)
HR 12 uint16 RW µs ×500
HR 13 uint16 RW DO - Pulse mode - status (0: Stop, 1: Start); bit n is channel n
HR 14 uint16 RW DI - Counter mode - status (0: Pause, 1: Run); bit n is channel n
HR 15 uint16 RW DI - Counter mode - clear overflow flag (1: Clear); bit n is channel n
IR 0 uint16 R DI - DI mode - status (0: OFF, 1: ON); bit n is channel n
IR 1 uint16 R DI - Counter mode - overflow flag (0: Normal, 1:; bit n is channel n
IR 2 uint16 R DI - mode (0: DI, 1: Counter); bit n is channel n
IR 3 uint16 R DO - mode (0: DO, 1: Pulse); bit n is channel n

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