Moxa ioThinx 45MR-4420 Modbus register map
Also covers ioThinx 45MR-4420-T
4-channel analog output module for the ioThinx 4510 adapter
- Official
- 12 registers
- Modbus TCP
- Revision 3 · 2026-11-11
Official: Written from the manufacturer's documentation, but not tested on a device yet. Check the map against the manufacturer's documentation before you write to a live device. Tested it? Report a test.
Communication
- Protocol
- Modbus TCP
- Unit ID
- 1
- TCP port
- 502
- Byte / word order
- ABCD · bytes big-endian, words high first
- Addresses
- 0-based
Connection values are defaults: the device may be configured differently.
Map
- Registers
- 8 holding registers, 4 input registers
- Groups
- 3
- Translation tables
- 1
- Revision
- 3 · 2026-11-11
- Added
- ()
- File
- maps/moxa/iothinx-45mr-4420.mbmap.json · 4 KB · history
- SHA-256
- 22d91bfb419e657beb574fa35431a2fc740218815305921b23c92a5b13ff09c2
- Manufacturer
- moxa.com
Sources and notes
- ioThinx 4510 Series User's Manual · version 6.2, 2024-07 Appendix A, 45MR-4420 (-T) registers
Source: Moxa, ioThinx 4510 Series User's Manual, version 6.2 (July 2024), Appendix A (Modbus/TCP slave rules and register lists)
- Addresses are relative to the module: the Modbus address on the 4510 is the slot's base address (set on the Modbus page of the 4510 web console: reload the default addresses or edit them) plus the relative address given here, separately for coils, discrete inputs, holding registers and input registers. Modbus/TCP port 502 on the ioThinx 4510 adapter.
- The manual lists every parameter with a length: in bits for coils and discrete inputs, and in 16-bit registers for the others. A DWORD or REAL value takes two registers; a REAL is a 32-bit float. Per-channel entries here follow that: for example 8 registers of DWORD for 4 channels are four 32-bit values.
- The manual does not state the word order of the 32-bit values; big is assumed. The function codes are 1, 5 and 15 for coils, 2 for discrete inputs, 3, 6 and 16 for holding registers and 4 for input registers.
- Each 'All' register is a bit mask with one bit per channel.
| Area | Address | Name | Type | Access | Unit | Scale | Description |
|---|---|---|---|---|---|---|---|
| HR | 0 | uint16 | RW | AO - raw value | |||
| HR | 1 | uint16 | RW | ||||
| HR | 2 | uint16 | RW | ||||
| HR | 3 | uint16 | RW | ||||
| HR | 4 | uint32 ABCD | RW | AO - scaled value | |||
| HR | 6 | uint32 ABCD | RW | ||||
| HR | 8 | uint32 ABCD | RW | ||||
| HR | 10 | uint32 ABCD | RW | ||||
| IR | 0 | uint16 | R | AO - mode (0: disable, 1: 0-10 V, 2: 0-20 mA, 3: | |||
| IR | 1 | uint16 | R | ||||
| IR | 2 | uint16 | R | ||||
| IR | 3 | uint16 | R |
No registers match
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Help improve this map
- I tested it on a deviceReport whether it worked, even if you did not write the map.
- Suggest a correctionEdit the file on GitHub; it opens a pull request.
- Report a problemA wrong address, type, scale or byte order.
- Read the formatWhat each key of the file means (SPEC.md).